View EPF8074G_4834981.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ELECTRONICS INC.
10/100 LAN Interface Module for PC Card Applications EPF8074G
* Optimized for QSI6611/6612 PHY/MAC * * Guaranteed to operate with 8 mA DC bias at 70C on cable side * * Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards *
Electrical Parameters @ 25 C
OCL @ 70C 100 KHz, 0.1 Vrms 8 mA DC Bias Cable Side 350H 1-80 MHz Insertion Loss (dB Max.) 100 MHz 150 MHz 1-30 MHz Return Loss (dB Min.) 60 MHz 100 MHz Common Mode Rejection (dB Min.) 30-100 MHz 200 MHz 500 MHz Crosstalk (dB Min.) [Between Channels] 5-10 MHz 10-100 MHz
Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit -1 -1 * -2 -2 -3.5 -3 -18 -18 -12
Rcv Xmit -12 -10
Rcv Xmit Rcv Xmit Rcv Xmit Rcv -10 -38 -38 -30 -25 -20 -15 -40 -40
Isolation : 1500 Vrms * Cable Impedance : 100 * Rise Time : 3.0 nS Max. *
Schematic
Receive Channel RD+ 3 12 RX+ CT 7 TD+ 6 Transmit Channel 8 CT 9 TX-
RD- 2 1:1 CT 1
13 RX14 CT TD- 5 2:1 10 TX+
Package
A J
Pin 1 I.D. PCA EPF8074G Date Code Dim. Min. .790 .510 .074 .600 .003 .100 .660 .016 .008 .090 0 .025
Dimensions
(Inches) Max. Nom. .810 .530 .084 Typ. .020 Typ. .680 .022 .012 Typ. 8 .045 .040 .100 .085 .700 (Millimeters) Min. Max. Nom. 20.06 12.95 1.88 15.24 0.076 2.54 16.76 .406 .203 2.28 0 .635 20.57 13.46 2.13 Typ. .508 Typ. 17.27 .559 .305 Typ. 8 1.14 1.02 2.54 2.16 17.78
N
B
Q
Pad Layout
P
D E C
M
K L I G
A B C D E F G H I J K L M N P Q
H
F
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
CSF8074Ga Rev.
8/6/97
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com
ELECTRONICS INC.
10/100 LAN Interface Module for PC Card Applications EPF8074G
The circuit below is a guideline for interconnecting PCA's EPF8074G with QSI6611 and QSI6612 chip set for 10/100 Mb/s applications. Further details can be obtained from the chip manufacturer application notes. Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust the chip's supporting resistor to get at least 2.12V pk-pk across the transmit pins. It is recommended that system designers do not use the receiver side center tap to ground, via a capacitor. This may worsen EMI, specifically if the secondary "common mode termination" is pulled to chassis ground as shown. The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. The "common mode termination" load of 75 shown from the center taps of the secondary may be taken to chassis ground via a cap of suitable value. This depends upon user's design, EMI margin etc. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.05 inches away from the chip side pins of EPF8074G. There need not be any ground plane beyond this point. For best results, PCB designer should design the outgoing traces preferably to be 50 , balanced and well coupled to achieve minimum radiation from these traces.
Typical Application Circuit for UTP
+5V
9
100 100 39
1 2 3 6
75 50
10 12 6 13 5 7
TX+
QSI66 11 or QSI66 12
TX-
RJ45*
4 5
14 7 8 Node Pinout
RX+ RX25 25
25 25
3
75 50
2
8 High Voltage Capacitor
EPF8074G
Chassis Ground
CM Capacitor
Notes : * NIC Side is shown. Hub side connection will have crossover swapping pins 3-6 & 1-2.
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
CSF8074Gb Rev.
8/6/97
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com

▲Up To Search▲

Price & Availability of EPF8074G

	To Download EPF8074G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .